Digital System Designs and Practices: Using Verilog HDL and Fpgas
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System-on-a-chip (SoC) has become an essential technique to lower product costs and maximize power efficiency, particularly as the mobility and size requirements of electronics continues to grow. It has therefore become increasingly important for electrical engineers to develop a strong understanding of the key stages of hardware description language (HDL) design flow based on cell-based libraries or field-programmable gate array (FPGA) devices. Honed and revised through years of classroom use, Lin focuses on developing, verifying, and synthesizing designs of practical digital systems using the most widely used hardware description Language: Verilog HDL.
Chapter 1 Introduction.
1.2 Introduction to Verilog.
1.3 Module Modeling Styles.
Chapter 2 Structural Modeling.
2.1 Gate-Level Modeling.
2.2 Gate Delays.
2.4 Switch-Level Modeling.
Chapter 3 Dataflow Modeling.
3.1 Dataflow Modeling.
Chapter 4 Behavioral Modeling.
4.1 Procedural Constructs.
4.2 Procedural Assignments.
4.3 Timing Control.
4.4 Selection Statements.
4.5 Iterative (Loop) Statements.
Chapter 5 Tasks, Functions and UDPS.
5.3 System Tasks and Functions.
5.4 User-Defined Primitives.
Chapter 6 Hierarchical Structural Modeling.
6.2 generate Statement.
Chapter 7 Advanced Modeling Techniques.
7.1 Sequential and Parallel Blocks.
7.2 Procedural Continuous Assignments.
7.3 Delay Models and Timing Checks.
7.4 Compiler Directives.
Chapter 8 Combinational Logic Modules.
8.5 Magnitude Comparators.
8.6 A Case Study: Seven-Segment LED Display.
Chapter 9 Sequential Logic Modules.
9.2 Memory Elements.
9.3 Shift Registers.
9.5 Sequence Generators.
9.6 Timing Generators.
Chapter 10 Design Options of Digital Systems.
10.1 Design Options of Digital Systems.
10.2 PLD Modeling.
10.5 Practical Issues.
Chapter 11 System Design Methodology.
11.1 Finite-State Machine.
11.2 RTL Design.
11.3 RTL Implementation Options.
11.4 A Case Study: Liquid-Crystal Displays.
Chapter 12 Synthesis.
12.1 Design Flow of ASICs and FPGA-Based Systems.
12.2 Design Environment and Constraints.
12.3 Logic Synthesis.
12.4 Language Structure Synthesis.
12.5 Coding Guidelines.
Chapter 13 Verification.
13.1 Functional Verification.
13.3 Test Bench Design.
13.4 Dynamic Timing Analysis.
13.5 Static Timing Analysis.
13.6 Value Change Dump (VCD) Files.
13.7 A Case Study: FPGA-Based Design and Verification Flow.
Chapter 14 Arithmetic Modules.
14.1 Addition and Subtraction.
14.4 Arithmetic and Logic Unit.
14.5 Digital-Signal Processing Modules.
Chapter 15 Design Examples.
15.2 Data Transfer.
15.3 General-Purpose Input and Output.
15.5 Universal Asynchronous Receiver and Transmitter.
15.6 A Simple CPU Design.
Chapter 16 Design for Testability.
16.1 Fault Models.
16.2 Test Vector Generation.
16.3 Testable Circuit Design.
16.4 System-Level Testing.
Appendix A Verilog HDL Syntax.
A.2 Source Syntax.
A.4 Primitive Instances.
A.5 Module and Generated Instantiation.
A.6 UDP Declaration and Instantiation.
A.7 Behavioral Statements.
A.8 Specify Section.
The book is intended to be adopted in advanced undergraduate electives and fundamental graduate courses. The prerequisite is digital logic design coursework. It is structured so that it can be used as a sequence of fundamental and advanced courses such as Hardware Description Language, FPGA System Designs and Practices, Digital System Designs, Advanced Digital System Designs, and others.
The secondary market is comprised of design engineers who want to increase their familiarity with Verilog HDL and FPGAs.