Digital Design and Verification using Verilog and SystemVerilog

Description

Digital Design and Verification using Verilog and SystemVerilog is an essential guide for students and early career professionals aiming to master the intricacies of digital design and verification. Authored by industry experts and academics, this book combines practical insights from the field with foundational teaching principles, making it a comprehensive resource for learning and applying Verilog and SystemVerilog.

About the Author

Sanjay Churiwala holds a B.Tech in Electronics and Electrical Communications Engineering from IIT Kharagpur. With over 30 years of experience in VLSI front-end design methodologies and Electronic Design Automation, he has extensively worked on Verilog-based designs in various roles, including Applications Engineering, Design and Verification Lead, and Tool Development and Verification. He holds several international patents and has authored numerous technical books on VLSI and related fields. Currently, he serves as the Corporate Vice President at AMD's Hyderabad office. Sanjay is also a regular guest lecturer on VLSI topics at various academic institutions.

Usha Mehta is currently a Professor and Head of the Department of Electronics and Communication, Institute of Technology, Nirma University, Ahmedabad. She has more than 24 years of teaching experience. She has guided more than ten research students. She has one Patent on her credit. She has been the Principal Investigator for research projects of DST-MeitY-C2S Scheme, ISRO RESPOND and GUJCOST. RHBD Chip developed for SAC, ISRO during this project has been fabricated at SCL, Chandigarh. She has published more than 55 research papers in areas of Digital System Design, VLSI Design and Testing.

Vaishali Dhare is an Assistant Professor in the Electronics and Communication Engineering Department at the Institute of Technology, Nirma University, Ahmedabad. Dr. Vaishali completed her PhD in Testing of Nanotechnology Devices and Circuits from Nirma University in 2018.

With over 20 years of teaching experience, she has guided more than 30 MTech and BTech projects and conducted various seminars and workshops. She has published over forty papers in journals and conference proceedings and is currently guiding two research scholars. She has also undertaken consultancy and research projects. Her areas of interest include Hardware Description Languages, Testing and Verification of VLSI Design, Quantum-dot Cellular Automata, Applied Algorithms for VLSI CAD, and Reversible Logic.

Table of Contents

Book Review

Chapter 1 Introduction to Verilog

Overview

1.1 History of Verilog

1.2 IP-Based Flows

1.3 Mixed Language Tools

1.4 Learning Verilog

1.5 Testbench

Chapter 2 Basic Concepts

Overview

2.1 Concurrent Execution

2.2 Hierarchy

2.3 Value and Signal Strength

2.4 Data Types

2.5 Variable Naming

2.6 Basic Structure of A Verilog Code

2.7 Simulation and Synthesis

Chapter 3 Modeling Levels

Overview

3.1 Introduction to Levels of Abstraction

3.2 Behavioural Modeling Style

3.2.1 initial and always Statements

3.3 Register Transfer–Level Modeling Style (Aka Data Flow Modeling)

3.4 Structural Modeling

3.5 Gate-Level Modeling

3.6 Switch-Level Modeling

Chapter 4 Modeling of Combinational Circuits

Overview

4.1 Verilog Primitives

4.2 Continuous Assignment

4.3 Modeling of Latches

4.4 ASIC vs FPGA Synthesis

Chapter 5 Branching Control

Overview

5.1 Controlling Statement: if-else-if

5.2 Case Statement for Multiway Branching

5.3 Unique and Parallel

Chapter 6 Procedural Blocks

Overview

6.1 initial Block

6.2 always Blocks

6.3 Modeling Flops

6.4 Modeling Latches

6.5 Variants of always Blocks

6.6 Synthesis considerations

6.7 Blocking Non-Blocking Assignments

6.8 Reentrance of always Blocks

6.9 Named Events

Chapter 7 Loop Control

Overview

7.1 Introduction

7.2 for Loop

7.3 while Loop

7.4 repeat Loop

7.5 forever Loop

Chapter 8 Understanding Race

Overview

8.1 read-write Race

8.2 write-write Race

8.3 initial-always Race

8.4 fork-join Races

8.5 Process Interleaving

8.6 Implications of Races

8.7 Avoiding Races

8.8 Testbench Created Races

8.9 Location of Race Origin

8.10 Event Scheduling Regions

Chapter 9 Modeling Synchronous Memories

Overview

9.1 Memory Basics

9.2 Simplest Memory Model

9.3 Parameterized Memory

9.4 Multi-Port Memory

9.5 Accessing Memory Contents in Bulk

9.6 Memory Test Patterns

9.7 Memory Corruption

9.8 Synthesis Considerations

9.9 Modeling Timing

Chapter 10 Parameterization

Overview

10.1 Parameter

10.2 Parameter Override

10.3 Local Parameter

10.4 Parameterized Memory Modeling

10.5 Specparam

Chapter 11 FSM Modeling

Overview

11.1 Introduction to Finite State machine

11.2 Digital System Design Using Finite State Machine

11.3 Synchronous Circuit Design Using Moore FSM

11.4 Design of Moore FSM Using Verilog

11.5 Synchronous Circuit Design Using Mealy FSM

11.6 Design of Mealy FSM Using Verilog

11.7 Comparison of Moore and Mealy FSM

Chapter 12 Hierarchical Models

Overview

12.1 Basic Concept of Hierarchy

12.2 Array of Instances

12.3 Conditional Instantiation

12.4 Instance Names Display

12.5 Escaped Names

12.6 Cross Module References

Chapter 13 User-Defined Primitives

Overview

13.1 User-Defined Primitives

13.2 Combinational User-Defined Primitives

13.3 Level-Sensitive Sequential User-Defined Primitives

13.4 Edge-Sensitive Sequential User-Defined Primitives

13.5 Combination of Level and Edge Sensitive Sequential User-Defined Primitives

13.6 Entries for Pessimism Reduction

Chapter 14 Switch Models

Overview

14.1 mos Switch

14.2 cmos Switches

14.3 Pass Switches

14.4 Strength Modeling

Chapter 15 Modeling Timing

Overview

15.1 Continuous Assignment Delay

15.2 Delays in Procedural Blocks

15.3 specify Block

15.4 Pulse Control

15.5 specparam

15.6 SDF Annotation

Chapter 16 System Function and Tasks

Overview

16.1 Introduction

16.2 System Tasks for File Handling

16.3 System Tasks for Writing in the File

16.4 System Tasks for Value Change Dump (VCD) File

16.5 System Tasks for Simulation Control

Chapter 17 Compiler Directives

Overview

17.1 `timescale

17.2 `include

17.3 `define

17.4 `ifdef, `elsif, `else, `ifndef, `endif

17.5 `celldefine, `endcelldefine

17.6 `resetall

Chapter 18 Functions and Tasks

Overview

18.1 Function Definition

18.2 Calling a Function

18.3 Automatic Functions

18.4 SystemVerilog Functions

18.5 Difference Between Functions and Tasks

18.6 Task Definition

18.7 Invoking a Task

18.8 Automatic and Static Tasks

18.9 Functions vs Tasks

18.10 Synthesis Considerations

Chapter 19 Design Verification

Overview

19.1 Introduction

19.2 Difference Between Verification, Validation, and Testing

19.3 Verification at Different Abstraction Level of ASIC Design Flow

19.4 Verification Flow

19.5 Verification Methods

19.6 Testbench Architecture

19.7 Verification Coverage Metrics

Chapter 20 SystemVerilog for Design and Verification

Overview

20.1 Evolution of SystemVerilog

20.2 Data Types of SystemVerilog

20.3 Arrays of SystemVerilog

20.4 Operators of SystemVerilog

20.5 Procedural Statements and Control Flow

20.6 Design Using SystemVerilog

20.7 Verification Using SystemVerilog