Embedded Systems: A Contemporary Design Tool, 2ed, An Indian Adaptation
ISBN: 9789357463966
892 pages
For more information write to us at: acadmktg@wiley.com
Description
This Indian edition enhances the coverage with new and updated content. It introduces a new chapter on Embedded Systems, new sections on an SDRAM Design, and Time Constraint and Divided Handling: Two-Level Elements. Additionally, a new appendix on Design Projects, representing simplified examples of real-world applications has been added. Many examples and exercises throughout the book are new or revised. It also includes multiple-choice questions derived from various competitive examinations.
0 Introduction to Embedded Systems 0.1 Introduction 0.1.1 Philosophy 0.1.2 What Is an Embedded System? 0.1.3 Building an Embedded System 0.2 Embedded Systems Versus General Computing Systems 0.3 Examples of Embedded Systems 0.4 The Embedded System Design and Development Process 0.4.1 Embedded System Design Stages 0.5 Conclusion 0.6 Summary 0.7 Multiple Choice Questions 0.8 Review Questions PART 1 Hardware and Software Infrastructure 17 Part 1 Hardware and Software Infrastructure 1 Memories and the Memory Subsystem 1.1 Introduction 1.2 Classifying Memory 1.3 A General Memory Interface 1.4 ROM Overview 1.4.1 Read Operation 1.5 Static RAM Overview 1.5.1 Write Operation 1.5.2 Read Operation 1.6 Dynamic RAM Overview 1.6.1 Read Operation 1.6.2 Write Operation 1.6.3 Refresh Operation 1.7 Chip Organization 1.8 Terminology 1.9 A Memory Interface in Detail 1.10 An SRAM Design 1.10.1 The Memory Array 1.10.2 Reading and Writing 1.10.3 Write 1.10.4 Read 1.11 A DRAM Design 1.11.1 DRAM Timing Analysis 1.11.1.1 Core Components 1.11.2 DRAM Refresh 36 1.12 The DRAM Memory Interface 1.12.1 Refresh Timing 1.12.2 Refresh Address 1.12.3 Refresh Arbitration 1.13 An SDRAM Design 1.13.1 Reading and Writing 1.13.2 Burst Mode Transfer 1.14 The Memory Map 1.15 Memory Subsystem Architecture 1.16 Basic Concepts of Caching 1.16.1 Locality of Reference 1.16.2 Cache System Architecture 1.17 Designing a Cache System 1.17.1 A High-Level Description 1.18 Caching – A Direct Mapped Implementation 1.19 Caching – An Associative Mapping Cache Implementation 1.20 Caching – A Block-Set Associative Mapping Cache Implementation 1.21 Dynamic Memory Allocation 1.21.1 Swapping 1.21.2 Overlays 1.21.3 Multiprogramming 1.21.3.1 Fixed 1.21.3.2 Variable Number 1.22 Testing Memories 1.22.1 RAM Memory 1.22.2 ROM Memory 1.23 Summary 1.24 Multiple Choice Questions 1.25 Review Questions 1.26 Problems 2 An Introduction to Software Modeling 2.1 Introduction 2.2 An Introduction to UML 2.3 UML Diagrams 2.4 Use Cases 2.4.1 Writing a Use Case 2.5 Class Diagrams 2.5.1 Class Relationships 2.5.1.1 Inheritance or Generalization 2.5.1.2 Interface 2.5.1.3 Containment 2.6 Dynamic Modeling with UML 2.7 Interaction Diagrams 2.7.1 Call and Return 2.7.2 Create and Destroy 2.7.3 Send 2.8 Sequence Diagrams 2.9 Fork and Join 2.10 Branch and Merge 2.11 Activity Diagram 2.12 State Chart Diagrams 2.12.1 Events 2.12.2 State Machines and State Chart Diagrams 2.12.2.1 UML State Chart Diagrams 2.12.2.2 Transitions 2.12.2.3 Guard Conditions 2.12.2.4 Composite States 2.13 Dynamic Modeling with Structured Design Methods 2.13.1 Brief Introduction to the Structured Design Philosophy 2.13.2 Data and Control Flow Diagrams 2.13.2.1 The Elements 2.14 Summary 2.15 Multiple Choice Questions 2.16 Review Questions 2.17 Problems 3 The Software Side – The Fundamentals of C 3.1 Introduction 3.2 Software and Its Manifestations 3.2.1 Combining Hardware and Software 3.2.2 High-Level Language 3.2.3 Preprocessor 3.2.4 Cross Compiler 3.2.5 Assembler 3.2.6 Linker and Loader 3.2.7 Storing 3.3 An Embedded C Program 3.3.1 A Program 3.3.2 Developing Embedded Software 3.3.2.1 Abstraction 3.4 C Building Blocks 3.4.1 Fundamental Data – What’s in a Name? 3.4.1.1 Identifiers in C 3.4.2 Defining Variables – Giving Them a Name and a Value 3.4.3 Defining Variables – Giving Them a Type, Scope, and Storage Class 3.4.3.1 Type 3.4.3.2 The const Qualifier 3.4.3.3 Variable Names Revisited 3.4.3.4 Type Conversions 3.4.3.5 Scope 3.4.3.6 Storage Class 3.5 C Program Structure 3.5.1 Separate Compilation 3.5.2 Translation Units 3.5.3 Linking and Linkage 3.5.3.1 Linking 3.5.3.2 Linkage 3.5.4 Where C Finds Functions 3.5.5 Makefiles 3.5.6 Standard and Custom Libraries 3.5.7 Debug and Release Builds 3.6 Operators in C 3.6.1 Arithmetic Operators 3.6.2 Assignment Operators 3.6.3 Comparison/Relational Operators 3.6.4 Logical Operators 3.6.5 Bitwise Operators 3.6.5.1 Bit Manipulation Operations 3.6.5.2 Testing, Resetting, and Setting Bits 3.6.5.3 Arithmetic Operations 3.6.6 Miscellaneous Operators 3.6.7 Precedence of Operators in C 3.7 Pointer Variables and Memory Addresses 3.7.1 Getting Started 3.7.2 Simple Pointer Arithmetic 3.7.2.1 Pointer Comparison 3.7.3 Const Pointers 3.7.4 Generic and Null Pointers 3.7.4.1 Generic Pointers 3.7.4.2 Null Pointers 3.8 The Function 3.8.1 Defining a Function 3.8.1.1 Function Header 3.8.1.2 Function Name 3.8.1.3 Arguments or Parameter List 3.8.1.4 Return 3.8.1.5 The Function Body 3.8.2 Using a Function 3.8.3 Pass By Value 3.8.4 Pass By Reference 3.8.5 Function Name Scope 3.8.6 Function Prototypes 3.8.7 Nesting Functions 3.9 Pointers to Functions 3.10 Structures 3.10.1 The Struct 3.10.2 Initialization 3.10.3 Access 3.10.4 Operations 3.10.5 Structs as Data Members 3.10.5.1 Accessing Members 3.10.5.2 Initialization and Assignment 3.10.5.3 Functions 3.10.6 Pointers to Structs 3.10.6.1 Accessing Members 3.10.7 Passing Structs and Pointers to Structs 3.11 The Interrupt 3.11.1 The Interrupt Control Flow 3.11.2 The Interrupt Event 3.11.3 The Interrupt Service Routine – ISR 3.11.3.1 Time Constraint 3.11.3.2 Divided Handling: Two-Level Elements 3.11.4 The Interrupt Vector Table 3.11.5 Control of the Interrupt 3.11.5.1 Enable–Disable 3.11.5.2 Recognizing an Interrupting Event 3.11.5.3 Interrupting and Masking an Interrupting Event 3.12 Summary 3.13 Multiple Choice Questions 3.14 Review Questions 3.15 Problems Part 2 Developing the Foundation 4 System Design Constraints – Safety, Security, Reliability, and Robust Design 4.1 Introduction 4.2 Safety 4.3 Reliability 4.4 Faults, Errors, and Failures 4.5 Another Look at Reliability 4.6 Some Real-World Examples 4.6.1 Big Word … Small Register 4.6.2 It’s My Turn – Not Yours 4.6.3 Where Do I Put My Stuff? 4.7 Single-Point and Common Mode Failure Model 4.8 Safe Specifications 4.9 Safe, Secure, and Robust Designs 4.9.1 Understanding System Requirements 4.9.2 Managing Essential Information 4.9.3 The Review Process 4.9.4 Bug Lists 4.9.5 Errors and Exceptions 4.9.6 Use the Available Tools 4.10 Safe and Robust Designs – The System 4.11 System Functional Level Considerations 4.11.1 Control and Alarm Subsystems 4.11.2 Memory and Bus Subsystems 4.11.3 Data Faults and the Communications Subsystem 4.11.4 Power and Reset Subsystems 4.11.5 Peripheral Device Subsystems 4.11.6 Clock Subsystem 4.12 System Architecture Level Considerations 4.12.1 Fail Operational2/Fail Operational Capability 4.12.1.1 Same Design 4.12.1.2 Alternative Designs 4.12.2 Reduced Capability 4.12.2.1 Lightweight Redundancy 4.12.2.2 Monitor Only 4.13 Busses – The Subsystem Interconnect 4.13.1 The Star Configuration 4.13.2 The Multidrop Bus Configuration 4.13.3 The Ring Configuration 4.14 Data and Control Faults – Data Boundary Values 4.14.1 Type Conformance 4.14.2 Boundary Values 4.15 Data and Control Faults – The Communications Subsystem 4.15.1 Damaged Data 4.15.1.1 Detectability 4.15.1.2 Extent 4.15.1.3 Response 4.15.2 Managing Damaged Data 4.15.2.1 Parity 4.15.2.2 Linear Codes 4.16 The Power Subsystem 4.16.1 Full Operation 4.16.2 Reduced Operation 4.16.3 Backup Operation 4.17 Peripheral Devices – Built-In Self-Test (BIST) 4.17.1 Self-Tests 4.17.2 Busses 4.17.3 ROM Memory 4.17.4 RAM Memory 4.17.4.1 Peripheral Devices 4.17.4.2 What to Do If a Test Fails? 4.18 Failure Modes and Effects Analysis 4.19 Security – Look Behind You 4.20 Understanding the Problem – Looking at the System 4.21 Analyzing the Problem – Looking at Potential Vulnerabilities 4.22 Understanding the Problem – Looking at the Attacks 4.22.1 Looking at the Software 4.22.2 Looking at the Hardware 4.23 Dealing with the Problem – Protecting Against the Attacks 4.23.1 Protecting the Software 4.23.1.1 First Steps 4.23.1.2 Second Steps 4.23.1.3 Third Steps 4.23.1.4 Fourth Steps 4.23.2 Software Testing Tools 4.23.3 Protecting the Hardware 4.23.3.1 First Steps 4.23.3.2 Second Steps 4.23.3.3 Third Steps 4.23.4 Protecting a Network Interface 4.23.4.1 First Steps 4.23.4.2 Second Steps 4.23.5 Firewall 4.24 Closure 4.25 Recent Trends 4.26 Summary 4.27 Multiple Choice Questions 4.28 Review Questions 4.29 Problems 5 Embedded Systems Design and Development – Hardware–Software Co-Design 5.1 Introduction 5.2 System Design and Development 5.2.1 Getting Ready – Start Thinking 5.2.2 Getting Started 5.3 Life-Cycle Models 5.3.1 The Waterfall Model 5.3.2 The V Cycle Model 5.3.3 The Spiral Model 5.3.4 Rapid Prototyping – Incremental 5.4 Problem Solving – Six Steps to Design 5.5 Hardware–Software Co-Design 5.5.1 The First Steps 5.5.2 Traditional Embedded Systems Development 5.6 History 5.6.1 Advantages of the Co-Design Methodology 5.7 Co-Design Process Overview 5.8 The Co-Design Process 5.9 Laying the Foundation 5.10 Identifying the Requirements 5.11 Formulating the Requirements Specification 5.11.1 The Environment 5.11.1.1 Characterizing External Entities 5.11.2 The System 5.11.2.1 Characterizing the System 5.12 The System Design Specification 5.12.1 The System 5.12.2 Quantifying the System 5.13 System Requirements Versus System Design Specifications 5.14 Executing the Hardware–Software Co-Design Process 5.15 Functional Decomposition 5.15.1 Identifying the Functions 5.15.2 Functional Decomposition 5.16 Partitioning and Mapping to an Architecture 5.16.1 Initial Thoughts 5.16.2 Coupling 5.16.3 Cohesion 5.16.4 A Few More Considerations 5.16.5 Approaches to Partitioning and Mapping 5.16.5.1 The Approach 5.16.5.2 The Method 5.16.6 Evaluation of a Partition 5.17 Architectural Design 5.17.1 Mapping Functions to Hardware 5.17.2 Hardware and Software Specification and Design 5.17.2.1 Developing the Architecture 5.18 Functional Model Versus Architectural Model 5.18.1 The Functional Model 5.18.2 The Architectural Model 5.18.3 The Need for Both Models 5.19 Modeling Tools and Languages for Co-Design 5.19.1 Why Are We Modeling? 5.19.2 What Are We Modeling? 5.19.3 Characterizing the Model 5.19.4 Classes of MoCs 5.19.4.1 Conceptual Model 5.19.4.2 Analytic Model 5.19.5 A Look at Some Models 5.19.5.1 The Logic Circuit 5.19.5.2 The Random Access Machine – RAM 5.19.5.3 The Turing Machine 5.19.5.4 The Pushdown Automaton Machine 5.19.5.5 The Basic Finite State Machine 5.19.5.6 Communicating Finite State Machines 5.19.5.7 Extended FSM 5.19.5.8 Co-Design FSM 5.19.5.9 Program State Machines 5.19.5.10 UML State Charts 5.19.5.11 Petri Nets 5.19.5.12 Kahn Process Network 5.19.5.13 Control Flow – Data Flow –CDFG Graphs 5.20 Co-Synthesis 5.20.1 Constraints 5.20.2 Software Synthesis 5.20.2.1 System Characterization 5.20.2.2 Scheduling 5.20.2.3 Synthesis Methods 5.21 Implementing the System 5.21.1 Analyzing the System Design 5.21.1.1 Static Analysis 5.21.1.2 Dynamic Analysis 5.22 Co-Simulation 5.22.1 Tools Supporting Modeling 5.22.2 Types of Simulations 5.22.3 Approaches 5.22.3.1 Detailed Processor Model 5.22.3.2 Cycle-Based Simulation – Bus Model 5.22.3.3 Instruction Set Architecture – ISA Model 5.22.3.4 Compiled Model 5.22.3.5 Hardware Model 5.22.3.6 Master Slave Model 5.22.3.7 Distributed Co-Simulation 5.22.3.8 Heterogeneous Modeling –The Ptolemy Project 5.22.3.9 Domains 5.22.3.10 Classes of MoCs 5.23 Co-Verification 5.23.1 Hardware–Software Co-Verification 5.23.2 Tools Supporting Simulation and Verification 5.23.2.1 Basic Capabilities 5.23.2.2 Levels of Abstraction 5.24 Other Considerations 5.24.1 Capitalization and Reuse 5.24.1.1 Capitalization 5.24.1.2 Reuse 5.24.2 Requirements Traceability and Management 5.24.2.1 Requirements Traceability 5.24.2.2 Requirements Management 5.25 Archiving the Project 5.26 Summary 5.27 Multiple Choice Questions 5.28 Review Questions 5.29 Problems &n
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